1. Field of the Invention
The present invention relates to a silicon carbide (SiC) substrate and a vertical semiconductor device using such substrate and to a manufacturing method thereof. More particularly, it relates to the art of reducing forward resistance.
2. Description of the Related Art
A vertical semiconductor device is known in which a current in a device runs from the first main surface to the second main surface of the device. The performance of the semiconductor device of this type is primarily determined by the structure of a device which is formed in an epitaxial layer formed on the surface of a substrate, and the substrate serves to hold the epitaxial layer and maintain its mechanical strength.
For example, a conventional Schottky barrier silicon carbide (SiC) diode comprises an n-type SiC substrate, an SiC homoepitaxial layer formed on the surface of the substrate, anode (electrode) further formed thereon, and a cathode (electrode) formed on the backside of the n-type SiC substrate.
In the case of the vertical semiconductor device, the resistance of a drift layer is determined by measuring the I-V characteristics between the anode and cathode. Its resistance is expressed as a sum of (surface contact resistance a)+(drift layer resistance b)+(substrate resistance c)+(backside surface contact resistance d). That is, the breakdown resistance of the device is only determined by the drift layer resistance b, but for forward resistance, (surface contact resistance a)+(substrate resistance c)+(backside surface contact resistance d) are added to the drift layer resistance b. It is therefore necessary to particularly reduce (substrate resistance c)+(backside surface contact resistance d) that are formed on the backside surface.
To this end, an attempt has been made to reduce the thickness of the substrate, or to increase the concentration of impurities in the backside surface of the substrate to reduce the contact resistance. However, in the former thickness reduction, there is a fear that the thin substrate may crack during a device fabrication process after the formation of the thin substrate, so that the thickness reduction has to be carried out after the formation of a semiconductor upper structure. In the latter case, an increase of concentration can be normally achieved by ion implantation and the following activation anneal, and an anneal at 1500° C. or higher, in the case of SiC, is required for activation. Therefore, a process using a material which receives a bad influence, has to be carried out after the anneal, and it has been impossible to reduce the thickness of the substrate and increase the concentration. Consequently, nothing has been particularly done to give priority to one of the above options and consider an approach to the other option together.
On the other hand, there has been a proposal to use a substrate in which a high-concentration layer is formed on the backside to reduce contact resistance, and form an electrode material on the high-concentration layer (refer to JP-A 2003-86816 [KOKAI]).
However, the technique in the above KOKAI Publication is also incapable of eliminating the resistance inherent in the substrate. As a commercially available 4H-SiC wafer for vertical power devices has a thickness of about 400 μm and a resistivity of about 0.020 Ωcm, the substrate has a resistance of 0.8 Ωcm2. The forward resistance of an SiC diode of a 1200 V class is several mΩcm2, so that the elimination of the substrate resistance, if possible, has a great effect. In addition, the contact resistance is usually as high as 0.1 mΩcm2 and the value in the whole wafer is nonuniformity-distributed, so that the reduction of the contact resistance is also required.
It has therefore been desired to obtain a thin SiC semiconductor substrate with a low resistance, and a semiconductor device using such a substrate.